Junction Depth Dependence of the Gate Induced Drain Leakage in Shallow Junction Source/Drain-Extension Nano-CMOS

This study describes the dependence of the surface electric field to the junction depth of source/drain-extension, and the suppression of gate induced drain leakage (GIDL) in fully depleted shallow junction gate-overlapped source/drain-extension (SDE). The GIDL can be reduced by reducing shallow junction depth of drain-extension. Total space charges are a function of junction depth in fully depleted shallow junction drain-extension, and the surface potential is proportional to these charges. Because the GIDL is proportional to surface potential, GIDL is the function of junction depth in fully depleted shallow junction drain-extension. Therefore, the GIDL is suppressed in a fully depleted shallow junction drain-extension by reducing surface potential. Negative substrate bias and halo doping could suppress the GIDL, too. The GIDL characteristic under negative substrate bias is contrary to other GIDL models. key words: GIDL, junction, halo, nanoscale CMOS